The delay device 10a of FIG. 1A also includes a first multi-bit wide latch 16 that is responsive to a strobe signal, shown as STORE1, which will be referred to herein as a first store signal. In response to a leading edge of the first store signal, the N-bit count value generated by the counter 14 will be latched into the first multi-bit wide latch 16. As described more fully hereinbelow, logic may be provided for automatically generating the reset signal RESET as a pulse to the counter 14 shortly before each active interval of the ring oscillator 12. This logic may also automatically generate the first store signal STORE1 as a pulse to the first multi-bit wide latch 16 shortly after each active interval of the ring oscillator 12. In this manner, the first multi-bit wide latch 16 will retain a regularly updated count value that is proportional to the number of consecutive oscillations of the ring oscillator 12 that occurred during a respective active time interval.
Two important specifications of a digital delay line are its resolution and its power supply noise immunity. The resolution is simply the accuracy with which the delay line can achieve the desired delay. If, for example, each delay element in a digital delay line has a 100 ps delay, then in an ideal case, of +/−50% delay variation, the actual delay provided by the delay line will be within ±50 ps of the desired delay and relatively few delay elements will be needed to provide the desired delay. In contrast, if each delay element has a 50 ps delay, then ideally the actual delay will be within ±25 ps of the desired delay, but more delay elements will be required to provide the desired delay. For high resolution, a small delay per stage is typically required. Power supply noise immunity has to do with the ability of a delay element to maintain an established delay in the presence of power supply and ground noise (including power supply level changes). A delay line which exhibits minimal change in delay in the presence of power supply and ground noise is important because changes in delay that result from unpredictable noise may cause significant undesirable changes in the output timing of the delay line. Efforts have been made to minimize power supply noise by using separate power supply pins that serve only the delay line when the device is packaged. However, because an integrated circuit chip substrate is commonly one of the power supply nodes, and because this node is typically common with the noise generating circuitry on the chip and the delay line, the use of separate power supply pins may not provide sufficient noise suppression. Other important specifications of a delay line are its power consumption and the total layout area required for its circuitry, which is generally proportional to transistor count.